The DDR-2 core with SSTL18 I/O interface buffer has pre-verified functionality, layout and timing closure combined with silicon validation.
The SSTL18 I/O buffer, with features including On-Die Termination (ODT), impedance controlled driver, and precision duty cycle matching, provide an electrical interface of superior signal integrity ensuring optimal performance and first pass success. The DDR-2 cores and SSTL18 I/O are immediately available for customer design-ins and are easy to integrate into an ASIC design.
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