With only a handful of qubits, it was possible to lead signals in from the outside world but, as qubit counts climb, good old reliable CMOS has been asked to take over the care work, with the added advantage that this keeps everything inside the cryostat.
At ISSCC 2021, Intel revealed details of a CMOS system chip (right) that runs at 4Kelvin, adjacent to a spin qubit cooled to 20mK.
What you need to cherish a spin qubit
The Intel SoC can actually drive up to 16 spin qubits by frequency multiplexing over a single RF line, as well as read the state of up to six qubits simultaneously (spin qubit readout here, and below, is based on RF single-electron transistor reflectometry) and control up to 22 gate potentials.
On-board is a microcontroller to add flexibility, but away from that controller, and the numerically-controlled oscillator, this is very much an RF chip with elaborate control over the profile and amplitude of output pulses. Intel chose a 22nm finfet process on which to build it.
There were three other cryo-CMOS papers, all from Europe, two from Delft University of Technology: a cryo-CMOS readout chip for spin qubits with 58dB gain and 0.6dB noise figure at 4.2K, and a 1Gsample/s switched capacitor ADC – thought to be the first fast cryo-ADC – that achieves 36.2dB SNDR to read multiple qubits for <0.5mW/qubit.
Delft dominated European papers at ISSCC this year, featuring in 12. KU Leuven made 6, IMEC and its cousins 4, EPFL 4, ETH Zurich 2, University College Dublin 2, then one each for CEA-Leti, University of Freiburg, University of Pisa, University of Twente and the University of Cambridge – that last one being the only UK university paper showing at ISSCC this year, coincidentally on the final cryo-CMOS paper, which was led by EPFL and Hitachi Cambridge, and also featured Quantum Motion Technologies of Leeds.
The EPFL/Hitachi paper covers a 40nm CMOS system chip (left) that, cooled to 3.5K, reads spin qubits using an intermediate-IF I/Q receiver operating at 5 – 6.5GHz with a 70dB gain and 0.55dB noise figure, and can read up to 70 qubits, dissipating 1.5mW/qubit.
In this case, the spin qubits are in quantum dots in the channels of FETs on a separate chip, made on the same 40nm standard CMOS process, cooled to 50mK.
It so happens that FET gate capacitance changes depending on the qubit state, and this is exploited by building an LC resonator close-up in the gate circuit, then sending a weak RF signal into the gate, whose reflection gets phase-modulated as the qubit changes – this is what is picked up by the read-out chip.
“The combination of such platforms, thanks to its scalability, integration and compactness, could form the basis for future silicon quantum computing systems,” according to EPFL’s presentation at ISSCC 2021.
ISSCC 2021 paper 13.1 A fully integrated cryo-CMOS SoC for qubit control in quantum computers capable of state manipulation, readout and high-speed gate pulsing of spin qubits in Intel 22nm FFL finfet technology
ISSCC 2021 paper 13.2 A fully-integrated 40-nm 5-6.5 GHz cryo-CMOS system-on-chip with I/Q receiver and frequency synthesizer for scalable multiplexed readout of quantum dots
ISSCC 2021 paper 13.3 A 6-to-8GHz 0.17mW/qubit cryo-CMOS receiver for multiple spin qubit readout in 40nm CMOS technology
ISSCC 2021 paper 13.4 A 1GS/s 6-to-8b 0.5mW/qubit cryo-CMOS SAR ADC for quantum computing in 40nm CMOS
To see what else was in the rest of ISSCC 2021, download the programme by clicking here
Images copied from ISSCC 2021 Digest with permission
